CAD for VLSI Design I

The below mentioned chapters cover the Front end design aspects of Very large Scale Integration Chip manufacturing Cycle. It also teaches verilog Hardware Description language (HDL) that shall help in describing a circuit to the tools for simulation and further processing of the same towards manufacturing the chip.

1. Evolution of CAD Tools
2. Importance of Design Automation
3. Basic Transistor Fundamentals
4. Gate Level Modeling
5. Higher Levels of Modeling
6. Types of CAD Tools
7. Verilog Quick Starter
8. Introduction to Simulators
9. Verilog Syntax
10. Verilog - Operators and expressions
11. Hierarchical Design and methodology
12. Delay modeling
13. Delay Modeling (contd)
14. Blocking and Non Blocking Assignments
15. Behavioural Modeling
16. Verilog Tasks and Functions
17. Memory Modeling
18. Advanced Delay Modeling
19. Advanced Delay Modeling (Contd)
20. Verilog Tricks
21. Introduction to Logic Synthesis
22. Logic Synthesis (Contd)
23. Logic Synthesis (Contd)
24. Synthesis: Assignment Statements
25. Synthesis: Arithmetic Operators
26. Synthesis: Bit Selects
27. Synthesis: Conditional Statements
28. Synthesis: Case Statements
29. Synthesis: Case Statements (Contd)
30. Synthesis: Loops
31. Synthesis: Local & Integer Variables
32. Synthesis: Flip Flops with preset / clear
33. Synthesis: Blocking Vs Non Blocking Assignments
34. Synthesis: Unknowns and High Impedance
35. Optimization in Synthesis
36. Optimization in Synthesis (Contd)
37. Introduction to Reconfigurable Computing
38. Introduction to FPGAs
39. Introduction to FPGAs (Contd)
40. The Altera Quartus Flow